An inverter assembly comprising a DC circuit, inverter means, and control means (CTRL) for controlling the inverter means, the inverter means being multilevel inverter means comprising a first half bridge (HB1) and a second half bridge (HB2), the control means (CTRL) being adapted to provide a first operating state in which the control means (CTRL) operate the inverter means as a full-bridge inverter. The control means (CTRL) are further adapted to provide at least one further operating state in which the control means (CTRL) operate the inverter means as a half-bridge inverter, the control means (CTRL) being adapted to select an operating state based on predetermined conditions.
