Descubra cinco bandas sul-coreanas para você se apaixonar e não tirar da playlist!

Day 6 was about Exceptions and handling those Exceptions in the kernel.

In RISC-V the CPU first checks medeleg register to determine which operation mode should handle the exception. In our case U-mode/S-mode is already handled by OpenSBI. Then, the CPU saves states into various CSRs. stvec register is set to pc then the exception is handled using the handler. Then sret is called…